As is well known, a solid state drive (SSD) is a data storage device that uses a non-volatile memory to store data. After data are written to the non-volatile memory, when no electric power is supplied to the non-volatile memory, the data are still retained in the solid state drive.
FIG. 1 is a schematic functional block diagram illustrating the architecture of a conventional solid state drive. As shown in FIG. 1, the solid state drive 10 comprises a control circuit 101 and a non-volatile memory 105. The non-volatile memory 105 is a NAND flash memory. Moreover, the non-volatile memory 105 comprises plural blocks Block_0, Block_1, . . . , and so on. One of the plural blocks is configured for storing a partial build table (also referred as a PBT table).
The control circuit 101 is in communication with a host 12 through an external bus 20. Consequently, commands and data can be exchanged between the control circuit 101 and the host 12. For example, the external bus 20 is a USB bus, an SATA bus, a PCIe bus, an M.2 bus, a U.2 bus, or the like.
In the solid state drive 10, the control circuit 101 is connected with the non-volatile memory 105 through an internal bus. According to a write command from the host 12, a write data from the host 12 is stored into the non-volatile memory 105 by the control circuit 101. Alternatively, according to a read command from the host 12, the control circuit 101 acquires a read data from the non-volatile memory 105 and transmits the read data to the host 12.
The control circuit 101 further comprises a logical-to-physical table 107. The logical-to-physical table 107 is also referred as a L2P table. The control circuit 101 can manage the data in the non-volatile memory 105 through the L2P table 107.
For updating the L2P table 107 in real time, the L2P table 107 is usually stored in a volatile memory. For example, the contents of the L2P table 107 are stored in a static random access memory (SRAM) or a dynamic random access memory (DRAM) that is included in the control circuit 101. Alternatively, the contents of the L2P table 107 are stored in a dynamic random access memory (DRAM) that is disposed outside the control circuit 101.
As mentioned above, the L2P table 107 is stored in a volatile memory. Consequently, when the solid state drive 10 is powered off, the contents of the L2P table 107 are lost. Before the solid state drive 10 is powered off, the control circuit 101 has to store the contents of the L2P table 107 into a specified location of the non-volatile memory 105. After the solid state drive 10 is powered off, the contents of the L2P table 107 in the control circuit 101 are lost but the contents of the L2P table 107 in the non-volatile memory 105 are still retained.
When the solid state drive 10 is powered on again, the contents of the L2P table 107 recorded in the specified location of the non-volatile memory 105 has to be loaded into the control circuit 101. After the contents of the L2P table 107 are loaded into the control circuit 101 successfully, the control circuit 101 can be operated normally.
If the electric power supplied to the solid state drive 10 is interrupted suddenly (i.e., a sudden power off event occurs) when the solid state drive 10 is in a working state, the contents of the L2P table 107 are lost. For solving this problem, the control circuit 101 performs a backup action when the solid state drive 10 is in the working state. Consequently, the contents of the L2P table 107 are updated and stored in the PBT table of the non-volatile memory 105.
Moreover, the data stored in the blocks of the non-volatile memory 105 can be deleted according to a trim command from the host 12. Generally, it takes a long time period to erase the stored data in the blocks. Consequently, when the control circuit 101 receives the trim command, the control circuit 101 does not perform an erase action immediately. That is, the data in the blocks are not erased immediately. Instead, the control circuit 101 performs a cancellation action on the L2P table 107. Subsequently, in a proper timing (e.g., a standby period), the control circuit 101 performs the erase action to completely erase the stored data in the blocks.
However, if the electric power supplied to the control circuit 101 is interrupted suddenly when the solid state drive 10 is in the working state, some drawbacks occur. For example, if the trim command has been issued from the host 12 to the control circuit 101 after the backup action is completed and before the sudden power off event occurs, the addresses corresponding to the cancellation action will be lost. Under this circumstance, the L2P table 107 cannot be accurately rebuilt by the control circuit 101.